The present invention relates to circuit board manufacture in general and more particularly to an improved etch resist in the form of a decal for hot stamping an image on copper or other substrate surface.
In recent years, there has been an accelerating trend towards simultaneous circuit size reduction and expansion of function in high performance electronic systems. Printed wiring board (PWB) technology has played an integral role in its evolution. Surface mount technology (SMT) has introduced new requirements in the design of PWBs, such as the use of substrates with fine lines and close spacing, small diameter plated through holes (PTH) and vias, and chip carriers with large numbers of fillet solder joints. In multi-layer printed wiring board construction (MLPWB), the evolution of PWB laminates (often composed of multiple thin laminates or "thin lams") has been prompted by greater device complexity, as well as the need to package these devices in a smaller volume. Maximum circuit integrity under adverse conditions also is a design criterion.
MLPWBs typically are constructed from a series of individual PWBs having insulative layers separating each PWB. Standard multi-layer boards, for example, can range from about 2 to 20 layers, each laminate ranging in dielectric thickness from about 1 to 250 mils. Conventional practice can adequately lay down artwork on each individual PWB followed by conventional etching and plating operations. Such conventional processing for the new generation of PWBs has been possible due to the flat, planar nature of conventional PWBs.
A recent development in circuit board manufacture involves the injection molding of three-dimensional circuit boards that require the circuits to traverse non-planar areas on the board and which have three-dimensional attachment portions for mounting other components to the board or mounting the board into an electrical unit. The three-dimensional nature of such injection molded circuit boards can be appreciated by reference to FIG. 2, for example. Conventional circuit processing techniques do not permit ramps and other non-planar areas to be conventionally imaged and certainly this is not feasible when structural attachment features are placed among the circuits on the board. Thus, new techniques for laying down circuits on these boards need to be developed.